1. Field of the Invention
The present invention relates to a synchronous semiconductor memory device capable of operating at a high clock frequency, such as a high-speed synchronous dynamic random access memory (SDRAM).
2. Description of the Related Art
In the reading of data from a memory cell in a high-frequency synchronous semiconductor memory device, and in the writing of data into the memory cell, the data must be reliably transmitted over data transmission lines having a large line capacitance. In particular, when the data transmission lines swing the full distance between the power supply potential (the high logic level) and the ground potential (the low logic level), read access must be preceded by an adequate equalization time.
To enable an adequate equalization time to be obtained at a high clock frequency, Japanese Unexamined Patent Application Publication No. 2001-155485 inserts selector switching elements between the data transmission lines and the input terminals of the preamplifier disposed at the end of the data transmission lines. The data are transmitted as pulses, during which the switching elements are placed in the conducting state or on-state to enable the preamplifier to detect the potential difference on the pair of data transmission lines. At the end of each data pulse, the switching elements are switched off and equalization of the data transmission lines begins. This enables the pair of data transmission lines to be brought to the same potential in preparation for the following read access, despite the large line capacitance and the high clock frequency.
The same problem is addressed in a different way by the conventional synchronous semiconductor memory device shown in FIG. 1, for example, by providing two complementary pairs of data transmission lines: a pair of read data bus lines RDB, RDBb and a pair of write data bus lines WDB, WDBb. This synchronous semiconductor memory device 500 comprises a timing control delay circuit 12, a column control clock generator 502, a column address predecoder 16, a column address decoder 18, a memory cell array 22, a data bus equalization controller 24, a read data bus (RDB) equalizer 504, a write data bus (WDB) equalizer 28, a read amplifier (AMP) controller 30, a read amplifier 506, a write driver controller 36 and a write driver 38. The memory cell array 22 comprises a plurality of memory cells 40, a plurality of sense amplifiers (SA) 42, a plurality of read column selection gates 44, and a plurality of write column selection gates 46. For simplicity, only one memory cell 40, sense amplifier 42, read column selection gate 44, and write column selection gate 46 are shown.
The timing control delay circuit 12 in this synchronous semiconductor memory device 500 delays an external clock signal 102 for a certain time to generate a delayed clock signal 104. Referring to FIG. 2, the column control clock generator 502 includes a pair of timing adjustment delay circuits 602, 606 that slightly delay both clock signals 102, 104. The column control clock generator 502 latches the rising edge of the delayed clock signal 104 in an RS flip-flop 610 comprising a pair of NAND gates 626, 628 to bring a column control clock signal 510 from the low logic level to the high logic level, and outputs the column control clock signal 510 through a pair of inverters 612 and 614. A one-shot pulse generator 608 comprising a buffer 620, an inverter 622, and a NAND gate 624 receives the following rising edge of the clock signal 102, and generates a one-shot pulse that resets the RS flip-flop 610, returning the column control clock signal 510 to the low logic level.
The column control clock signal 510 and a read signal 108 are supplied to the column address decoder 18, data bus equalization controller 24, read amplifier controller 30, and write driver controller 36. The column address predecoder 16 pre-decodes a column address signal 110 and outputs a predecoded address signal 112 to the column address decoder 18. In a read cycle, when the read signal 108 is at the high logic level, the column address decoder 18 generates a read column selection signal 114, and the memory cell data amplified by the sense amplifier 42 are output through bit lines 118, 120 and the read column selection gate 44 to the read data bus lines RDB, RDBb. In a write cycle, when the read signal 108 is at the low logic level, the column address decoder 18 generates a write column selection signal 116, and the data on the write data bus lines WDB, WDBb are written through the write column selection gate 46 and bit lines 118, 120 into a selected memory cell 40.
The data bus equalization controller 24, read amplifier controller 30, and write driver controller 36 control the data buses. The data bus equalization controller 24 generates a read equalization signal 122 and a write equalization signal 124, in response to which the read data bus equalizer 504 and write data bus equalizer 28 equalize the data bus lines. When the read signal 108 is high, the read amplifier controller 30 generates a read amplifier control signal 126 to activate the read amplifier 506, waiting for a certain time from the end of the equalization interval to allow an adequate potential difference to develop on the read data bus lines RDB and RDBb. When the read signal 108 is low, the write driver controller 36 generates a write driver control signal 132 to activate the write driver 38, starting as soon as the equalization interval ends.
The column selection signals 114, 116, the read equalization signal 122, the write equalization signal 124, the read amplifier control signal 126, and the write driver control signal 132 are synchronized to the column control clock signal 510 as shown in FIG. 3. The read equalization signal 122 is active throughout each write cycle, so the read data bus lines RDB, RDBb are thoroughly equalized before the following read cycle. In succeeding read cycles, the read data bus lines are equalized for intervals equal in length to the pulse width of the column control clock signal 510, which is determined solely by the timing control delay circuit 12 and the timing adjustment delay circuits 602, 606 in the column control clock generator 502. The write data bus is similarly equalized throughout read cycles, and for intervals equal in length to the pulse width of the column control clock signal 510 during write cycles. By equalizing the read data bus during write cycles, and the write data bus during read cycles, the synchronous semiconductor memory device 500 can prepare the data buses for reliable data transfer despite the large load presented by the bus lines, the bit lines 118, 120, and the many connected transistors (not shown) in the memory cell array 22.
During a write cycle, the write driver 38 must drive the write data bus lines for an adequate time to write the data through this load into the memory cell 40. The write driver 38 does not require a long equalization time, however, because it simply drives the write data bus lines WDB, WDBb to the necessary logic levels, regardless of whether they have been completely equalized or not.
In a read cycle, however, the read amplifier 506 must first detect a slight potential difference on the read data bus lines and then amplify the difference. This operation requires both an adequate preceding equalization time, to ensure that the potential difference is correctly detected, and an adequate amplification time. In a series of successive read cycles, the equalization time in the second and subsequent cycles is equal to the pulse width of the column control clock signal 510, as noted above. If this pulse width is comparatively short, as shown in FIG. 3, then at high clock frequencies, equalization may become inadequate, leading to possible read errors. If the pulse width of the column control clock signal 510 is lengthened, however, then the interval during which the write driver 38 is activated may is correspondingly shortened, leading to possible write errors.